Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Among the efforts for resolving the above-discussed limitations, three-dimensional integrated circuit (3DIC) and stacked dies are commonly used. Through-silicon vias (TSV) are often used in 3DIC and stacked dies for connecting dies. FIGS. 1 and 2 illustrate a conventional method for forming TSVs. Referring to FIG. 1, silicon substrate 2 is provided, on which integrated circuits (not shown) are formed. Dielectric layers 6, in which metal lines and vias (not shown) are formed, are then formed layer-by-layer over silicon substrate 2. Photo resist 8 is then applied and patterned. Opening 10 is formed through dielectric layers 6, exposing silicon substrate 2. Silicon substrate 2 is then etched through opening 10, forming opening 12, as shown in FIG. 2. A glue layer and/or a diffusion barrier layer (not shown) are formed on the sidewalls and the bottom of openings 10 and 12. Copper (not shown) is then filled by plating to form a through-silicon via.
The conventional TSV formation process suffers drawbacks. Since openings 10 and 12 are very deep compared to their width, the glue layer and the diffusion barrier layer have poor coverage on sidewalls of openings 10 and 12. Furthermore, it is hard to form void-free TSVs. Accordingly, the plating current for filling copper into openings 10 and 12 has to be reduced in order to reduce the likelihood of voids in TSVs, and hence the throughput is reduced.
To solve the above-discussed problems, openings 10 and 12, particularly opening 12, preferably have tapered profiles with upper portions wider than lower portions. This may be achieved by adjusting the etching recipe to increase lateral etching. However, this approach causes severe undercuts 14 underlying dielectric layers 6. Undercuts 14 cause the breaking in the subsequently formed diffusion barrier layer and a seed copper layer, and hence adversely affect the subsequent plating of copper.
Accordingly, what is needed in the art is a TSV structure and method for forming the same that take advantage of tapered profile of TSVs, while at the same time not incurring serious undercuts.